In existing memory systems, memory operations performed in response to memory commands are often performed in a sequential manner. Typically, the sequence in which a memory performs memory operations in response to the memory commands is a reflection of the sequence in which the memory receives commands.
This constraint of existing memory systems has led to challenges in implementing particular memory mechanisms, such as error detection and/or error correction. Indeed, some more recent specifications stipulate implementation of error detection and/or error correction in the form of a masked write command. Briefly, with existing memory architectures designed to sequentially perform memory operations it may be challenging to implement these mechanisms.